Department of Electronics and Telecommunication Engineering Padmabhushan Vasantdada Patil Institute of Technology is organizing a one week workshop on “VLSI Design Using Cadence Tool” in association with Entuple Technologies Pvt Ltd, Bangalore on 13th to 19th June, 2016.

This workshop will provide a platform for faculty of Engineering Institutes, researchers and students interested in teaching and research in the areas of VLSI Design (Analog/Digital) and ASIC Design to interact and upgrade their knowledge in the said field. The resource persons for the workshop are well experienced teams from Entuple, Bangalore.

This workshop will provide hands on  of CADENCE tool and will be good platform for researcher and teacher working in VLSI domain.

You are kindly invited for attending the workshop program. Please forward this mail and encourage your colleagues working in the said domain to participate in this workshop and make this workshop a grand success.

For more information and details please contact,